The present invention relates to a semiconductor device, and more particularly, to an internal voltage generation circuit for generating a voltage for use in a semiconductor device and a method therefor.
A Dynamic Random Access Memory (DRAM), a type of semiconductor device, uses internal voltages including a core voltage VCORE and a precharge voltage VBLP, in addition to a power supply voltage VDD from outside. Such an internal voltage or a voltage for generating another internal voltage, where an already generated internal voltage is reused to generate another internal voltage with a different level, is generated by an internal voltage generation circuit.
FIG. 1 is a schematic block diagram of a conventional internal voltage generation circuit. Referring to FIG. 1, the conventional internal voltage generation circuit includes a voltage generator 110, a code storage 120, and a decoder 130.
The voltage generator 110 generates a plurality of voltages having different levels by using an external voltage. The code storage 120 includes first to third code storing units 121 to 123 for storing selection codes FUSE<0:2> to select an internal voltage VREFC among the plurality of voltages and outputting it to the decoder 130. In the test mode, the code storage 120 outputs test selection codes TCM<0:2>, not the selection codes FUSE<0:2>, to the decoder 130. Then, the decoder 130 decodes the selection codes FUSE<0:2> or the test selection codes TCM<0:2> provided from the code storage 120 through nodes CUT<0:2> to select the internal voltage VREFC among the plurality of voltages. The operation, the selection codes FUSE<0:2> stored in the code storage 120 are used to set a level of an internal voltage VREFC, but in the test mode, the test selection codes TCM<0:2>, not the selection codes FUSE<0:2>, are used to select the level of an internal voltage VREFC.
FIG. 2 is a detailed circuit diagram of the first code storing unit 121 of FIG. 1, and FIG. 3 diagrammatically shows how a test mode signal are generated. Among the code storing units included in the code storage 120 in FIG. 1, the first code storing unit 121 is illustrated in FIG. 2. The second and third code storing units 122 and 123 only differ from the first code storing unit 121 in that TCM<1>, TCM<2>, FUSE<1>, and FUSE<2> are applied thereto.
In FIG. 2, a power-up signal PWRUP_P is a pulse signal that is generated while a power supply voltage VDD rises after power-up, wherein it is generated at about 1 V when VDD becomes about 1.8 V. This signal turns on a first NMOS transistor N01, and thus the voltage of a node A is initialized to a logic low level. Even though the voltage of the node A is initialized to a logic low level, its logic level varies after a certain amount of time, depending on whether a fuse which is a storing means has been cut. That is, if the fuse has not yet been cut, the voltage of the node A becomes a logic high level. However, if the fuse has been cut, the voltage of the node A becomes a logic low level. Because the voltage of the node A is inverted and then transferred to a node CUT<0>, if the fuse has been cut, the node CUT<0> becomes a logic high level; otherwise, the node CUT<0> becomes a logic low level.
A test mode signal TVCOSUM becomes a logic high level in a test mode, and is generated through a circuit shown in FIG. 3. If any one of test selection codes TCM<0:2> becomes a logic high level, the test mode signal TVCOSUM becomes a logic high level as well. When the test mode signal TVCOSUM becomes a logic high level, a first PMOS transistor P01 is turned on, so that the node A always becomes a logic high level. That is, whether the fuse has been cut or not has no influence on the node A. Thus, a ‘low’ signal is inputted to the upper terminal among input terminals of a NOR gate N001, and the output of the node CUT<0> becomes equal to the logic level of the test selection code TCM<0>.
In short, the code storage 120 outputs the selection codes FUSE<0:2> stored in its own storing units to the nodes CUT<0:2> in a normal mode. However, when even one of the test selection codes TCM<0:2> is enabled, the code storage 120 automatically enters the test mode and provides the test selection codes TCM<0:2> to the nodes CUT<0:2>.
FIG. 4 is a detailed circuit diagram of the decoder 130 of FIG. 1. Referring to FIG. 4, the decoder 130 decodes the selection codes FUSE<0:2> or the test selection codes TCM<0:2> transferred to the nodes CUT<0:2> outputted from the code storage 120, and outputs voltage selection signals CS<0:7> for selecting one of voltages to be generated by the voltage generator 110.
As shown in the drawing, the decoder 130 is constituted by a plurality of NAND gates NA01 to NA08 and a plurality of inverters I04 to I11, to which signals transferred to the nodes CUT<0:2> are inputted as they are (CUT<0:2>) or in inverted form (CUTB<0:2>). FIG. 6 shows when the voltage selection signals CS<0:7> are enabled.
FIG. 5 is a detailed circuit diagram of the voltage generator 110 of FIG. 1. The voltage generator 110 generates plural voltages 4UP, 3UP, 2UP, 1UP, BASE, 1DN, 2DN, and 3DN to be used as an internal voltage VREFC by a voltage division. The voltage generator 110 shown in the drawing receives a reference voltage VREF through an operational (OP) amplifier 510 whose output is feedbacked, and generates the plural voltages 4UP, 3UP, 2UP, 1UP, BASE, 1DN, 2DN, and 3DN through a voltage division using resistors R1 to R8.
Addressing voltage level, because two input terminals, i.e., the reference voltage VREF and a feedback voltage RFED of the OP amplifier 510, become equal, the feedback voltage RFED becomes equal to the reference voltage VREF. Therefore, a node 501 has a voltage twice the reference voltage, i.e., 2×VREF. The reference voltage VREF is insensitive to temperature and outputted from a bandgap circuit.
The plural voltages are coupled to a plurality of pass gates 521 to 528. The pass gates 521 to 528 are turned on/off by the voltage selection signals CS<0:7> from the decoder 130 and their inverted voltage selection signals CSB<0:7>, and a selected voltage is outputted as the internal voltage VREFC to be used in a semiconductor device.
FIG. 6 is a table describing logic values of the selection codes FUSE<0:2>, the test selection codes TCM<0:2>, and signals at the nodes CUT<0:2> thereby, and the voltage selection signals CS<0:7> that are decoded in the decoder 130 and enabled. It can be seen from FIG. 6 that the nodes CUT<0:2> has logic levels in the normal mode, i.e., the selection codes FUSE<0:2> determine logic levels of the signals at the nodes CUT<0:2>, and in the test mode, i.e., the test selection codes TCM<0:2> determine the logic levels of the signals at the nodes CUT<0:2>, and that voltage selection signals CS<0:7> are decoded to be enabled according to the logic levels of the signals at the node CUT<0:2>.
In general, a semiconductor device experiences variations in transistor characteristics by skew occurring during a process. The skew is generated due to thickness variation of the gate oxide, sheet resistance variation, gate length variation, gate width variation, etc. This characteristic changes the level of a voltage source, for example, which causes each wafer to have a different level.
The internal voltage VREFC suitable for a target voltage is selected by cutting or trimming the fuse, which is the code storing units of the internal voltage generation circuit described above, to store selection codes FUSE<0:2>. When a defect analysis is to be made because of a problem found in a package, it is necessary to conduct a test under variations of the internal voltage VREFC. At this time, the test selection codes TCM<0:2>, which is the test mode signal, is applied to select an internal voltage VREFC again.
In the conventional internal voltage generation circuit set forth above, however, there is no correlation between the selection codes FUSE<0:2> inputted onto the wafer and the test selection codes TCM<0:2> applied during the test. In effect, if the test selection codes TCM<0:2> are inputted, the selection codes FUSE<0:2> stored in the fuse are ignored.
A base level of the internal voltage VREFC previously set is important for an accurate analysis on defects caused by an increase/decrease in the internal voltage VREFC by variations thereof with respect to the base level at the time of defect analysis. However, the conventional internal voltage generation circuit requires the internal voltage VREFC to be set all over again for every test, with the result that it takes relatively long to obtain previous information and to process data at the time of defect analysis.